Multiphase Divider Explainer & Viva Defense Guide

For the team: read this first

A practical route through the guide and a shared preparation checklist.

Reading order

In one minute
The initial paper
Report section map
Timeline
Viva questions
Glossary

Our roles

Role	Name
Cadence simulation
Report writing
Theory assignment
Layout
Presentation
FPGA

What still needs to be done by each person

Agree on owners together. Checkmarks are saved only in this browser.

Students: fill in the blank cover-page register numbers and arrange signatures.
Replace remaining placeholders with the appropriate Cadence ADE, Virtuoso and layout screenshots.
Review the unsized process, voltage and temperature (PVT) analysis in the report's simulation and PVT results section. For the GPDK045 work, 26 of 45 corners divide.
If the team's 180 nm report is merged, check that technology, results, figures and conclusions remain consistent and clearly attributed across both reports.
Rehearse the viva together using the 15 questions in this guide.

Scan to open this guide on another device.

Section 01

In One Minute

The entire laboratory project and research investigation distilled into five clear statements and six core numbers.

What this project did: It implemented and characterized a compact eight-phase divide-by-two CMOS frequency divider in Cadence GPDK045 (45 nm, 1.0 V supply) based on the four-latch Current-Mode Logic (CML) ring architecture introduced by Kuo et al. in IEEE MWTL 2025 (originally fabricated in TSMC 180 nm at 1.8 V).
The discovery on transplantation: Direct transplantation of the reference paper's sizing rule (R1 = Ron / 2 = 1.15 kΩ) completely fails to divide at 45 nm, instead oscillating at 2799.8 MHz (2 · fin) with an unusable 15.3 mV swing because three stacked NMOS transistors require far higher regenerative load resistance.
The sizing solution: By establishing a 3·Ron / m series-stack regeneration heuristic (requiring Rload ≥ 1.1 · 3·Ron / m), state regeneration is restored, providing a dividing unit-size baseline U8k (m = 1, R = 8 kΩ) and two tuned sized configurations: Design D (m = 4, R = 3 kΩ at 1.4 GHz) and Design B (m = 4, R = 2 kΩ at 6.0 GHz).
Key performance results: Sized Design D consumes 0.5413 mW power (0.4554 mW in Virtuoso schematic netlist) with 0.4344 V swing and passes 41 of 45 PVT corners (91.1%), while Design B pushes frequency to 6.0 GHz with a low phase error of 3.78° (matching Kuo's 3.75° benchmark) and passes 21 of 45 PVT corners.
Honest physical status: The physical layout in Cadence Virtuoso Layout XL is placement-only (21 Assura DRC errors across 3 rules; 0 routed, 0 post-layout) because automated routing produced 134 DRC errors and the kit copy lacks Assura RCX extraction files; hence no LVS-clean or post-layout extraction claims are made.

Design D (1.4 GHz Input)

0.5413 mW

Output 700.0 MHz • Phase error 38.46° • Swing 0.4344 V • PDP 14.067 fJ

Virtuoso netlist: 0.4554 mW results/final/D_1p4.tsv

Design B (6.0 GHz Input)

3.78° Error

Output 3000.0 MHz • Power 0.4929 mW • Swing 0.1349 V • PDP 13.768 fJ

Matches Kuo benchmark (3.75°) results/final/B_6g.tsv

PVT Coverage: Design D

41 / 45 Pass

91.1% corner coverage (5 process × 3 temps × 3 voltages). Fails only at 125 °C, 0.9 V.

Deterministic corner count pvt_summary_D_1p4.json

PVT: Design B & U8k

21 / 45 & 26 / 45

Design B passes 21/45 at 6 GHz; U8k baseline passes 26/45 at 1.4 GHz. Paper rule passes 0/45.

High-frequency margin trade-off pvt_summary_B_6g.json

Physical Layout Status

21 DRC Errors

Placement-only layout across 3 Assura rules. Unrouted; no LVS, no RCX post-layout.

Router had 134 DRC errors assura_drc_dlatch_summary.txt

Technology & Supply

45 nm / 1.0 V

Cadence Virtuoso IC6.1.5 & Spectre MMSIM 12.1 in GPDK045 (standard-Vt NMOS).

Reference paper was 180 nm / 1.8 V spectre/divider_gpdk45.scs

Section 02

The Initial Paper, Explained

How Yue-Fang Kuo et al. (IEEE MWTL, May 2025) synthesized eight clock phases from a single differential input without inductors or frequency quadruplers.

The Core Problem & Conventional Limitations

Multiphase local oscillator (LO) clocks are essential components in modern phased-array transmitters (for beamforming phase-interpolation), harmonic-rejection mixers (to cancel 3rd and 5th harmonic spurs), and clock/data recovery circuits (CDR). However, classical methods have severe penalties:

Multistage LC-tank VCOs: Require bulky on-chip spiral inductors and varactor banks, occupying excessive die area and restricting tuning range.
Polyphase Filters (PPFs): Cascade RC polyphase stages to split phases, but suffer from high insertion loss, severe attenuation at gigahertz frequencies, and extreme vulnerability to process/temperature variations.
Cascaded Dividers: Traditional divide-by-two circuits produce only 4 quadrature phases from a differential input. Achieving 8 phases previously required 3 frequency dividers and a quadrupled input frequency (4 · fin) or a 4-phase input driver.

Kuo et al.'s Innovation: They inserted a second cascading D-latch pair into the feedback loop, creating a compact 4-latch closed ring. Controlled by a single differential clock (CK, CKb), this ring naturally outputs 8 discrete, equidistant 45° clock phases with zero inductors and zero polyphase filters, consuming only 91.7 × 52.9 µm² core area in TSMC 180 nm.

Diagram 1: Four-latch CML ring divider signal path and DLATCH internal transistor stack.

Circuit Architecture: The Four-Latch Ring

The divider consists of four differential Current-Mode Logic (CML) D-latches (XD1 to XD4). Two foundational design rules govern the topology:

Dual-Clock Phasing: Latches 1 & 4 receive true clock CK at their sampling switch (M5) and inverted clock CKb at their hold switch (M6). Latches 2 & 3 receive the exact inverse: CKb at sampling switch M5 and CK at hold switch M6. Thus, when CK is HIGH, Latches 1 & 4 sample while Latches 2 & 3 hold; when CK falls LOW, Latches 2 & 3 sample while Latches 1 & 4 hold.
Alternating Cross-Connections: The differential outputs connect to the subsequent inputs with alternating polarity:
- Latch 1 → Latch 2: Q1b → D2, Q1 → D2b (Crossed)
- Latch 2 → Latch 3: Q2 → D3, Q2b → D3b (Direct)
- Latch 3 → Latch 4: Q3b → D4, Q3 → D4b (Crossed)
- Latch 4 → Latch 1: Q4b → D1, Q4 → D1b (Long Feedback Crossed)

Net Loop Inversion & Division by Two: The inter-stage connections create an odd number of signal inversions around the four stages. Consequently, a digital transition must circulate through all four latches twice before returning to its original state. That requires exactly two full input clock periods (2 · TCK), yielding strict divide-by-two frequency division: fout = fin / 2.

Diagram 2: Timing waveforms and phasor wheel showing how 8 equidistant 45° phases arise across 2 input cycles.

The Elmore Delay Model & Edge-Balance Concept

Each DLATCH contains 7 NMOS transistors (M1–M7) and two symmetric resistive loads (R1, R2). In the paper's theoretical derivation (Section II, Eqs. 1–2), Kuo et al. model transient delays using Elmore RC time constants under two simplifying assumptions: tail transistor M7 is permanently on with its drain at AC ground (node-b ≈ 0 V), and unit gate capacitance equals junction capacitance (Cg = Cd = C):

Lumped Output Node Capacitance: Output node Q carries Ctotal = (6 + 2)C = 8C (drain junctions 2C, cross-coupled gate 1C, downstream latch gate 1C, and interconnect routing parasitics 4C).
Discharging Delay (Falling Transition t_pdf): Node Q discharges to ground through M1 and clock switch M5. With combined branch on-resistance modeled as R / 2, the Elmore fall delay is:
t_pdf = (8C) · (R / 2) = 4 · R · C (Paper Eq. 1)
Charging Delay (Rising Transition t_pdr): Node Q charges from VDD exclusively through pull-up load resistor R1:
t_pdr = (8C) · R1 (Paper Eq. 2)

Crucial Physical Insight: Edge-Balance vs. State Regeneration

Kuo et al. set t_pdr = t_pdf, concluding that R1 = Ron / 2. This is strictly an edge-balance condition to make rise and fall times symmetrical under a simplified grounded-tail model. It is NOT a regeneration condition. In physical CMOS, the cross-coupled hold pair (M3–M4) requires loop gain A_loop = gm · R1 > 1 to hold and regenerate logic states. If R1 is set too low (e.g. 1.15 kΩ in 45 nm), loop gain drops below unity, causing the divider to fail completely.

Speed Limit & Phase Accuracy Condition

For the divider to function, a digital signal transition must propagate through two latches (2 · Td) within half an input clock cycle (TCK / 2):

2 · Td < TCK / 2   ⟹   fin,max < 1 / (4 · Td)

To produce eight perfectly equidistant 45° phase outputs (where each output is spaced by Tout / 8 = TCK / 4), each latch must introduce a delay Td ≈ TCK / 8, meaning 2 · Td ≈ TCK / 4. As input frequency increases toward the maximum speed limit, the internal delay naturally approaches this fraction, causing adjacent phase error to drop toward zero (as evidenced in Design B at 6.0 GHz where phase error is 3.78°).

What Kuo et al. Measured in TSMC 180 nm Silicon

The original paper fabricated and evaluated a physical silicon die in TSMC 0.18 µm 1P6M CMOS at 1.8 V supply:

Operating Frequency: 100 MHz to 1.4 GHz (173.3% fractional frequency tuning range).
Power Consumption: 2.34 mW at 1.4 GHz from 1.8 V supply.
Phase Step Accuracy: Measured phase difference across the eight 700-MHz outputs was within 3.75°.
Physical Dimensions: Total die size 734 × 634 µm²; active divider core occupied only 91.7 × 52.9 µm² (four latches alone took 26.72 × 15.53 µm²).
Testing Setup: Custom octagonal PCB with equal-length microstrip lines; Keysight N5182B RF generator with balun and bias tees; Agilent DSO9104A 4-channel oscilloscope.

What Kuo et al. Did NOT Do

No PVT Corner Analysis: The paper reports only room-temperature, nominal-voltage lab bench measurements; no process corners (ff/ss/fs/sf), temperature sweeps (-40 °C to +125 °C), or voltage variations (±10%) were characterized.
No Deep Submicron Porting: Sizing rules were not tested on advanced nodes (such as 45 nm) where short-channel effects, lower supply headroom (1.0 V), and multi-transistor series stacks degrade regeneration.
No Tail Headroom Modeling: M7 was treated as an ideal current sink with a grounded drain node, overlooking triode operation and voltage headroom compression.
No Mismatch Statistics: Device mismatch and threshold voltage variations were not simulated with Monte Carlo distributions.

Section 03

What Our Report Did, Section by Section

A complete audit mapping of every required section in the institutional report format to our implementation, evidence files, and honest status chips.

Diagram 3: Simulation-to-Report Evidence & Verification Pipeline from Spectre MMSIM 12.1 to Report Delivery.

1. Institutional Title & Cover Block Done with caveat

Report Page 1 • Template Section: Institutional Header & Metadata Table

Includes department title, institutional logo, course codes (23ECE302 & 23ECE383), and double border. Student register numbers, names, batch number, and faculty signature lines remain blank underscores by design for student submission.

assets/amrita_logo.jpeg • report/gpdk045/System_Design_Project_Report_gpdk045.pdf (Page 1)

2. Title of the System Design Project Done

Report Page 2 • Template Section: Project Title

"Implementation of a Compact Multiphase Divide-by-Two CMOS Frequency Divider in 45 nm CMOS (Cadence GPDK045)". Stated verbatim without placeholder text.

report_data.json: titles.system_design_project

3. Details of the Paper (Source of Title) Done

Report Page 2 • Template Section: Source Paper Details

Complete citation of Yue-Fang Kuo et al., IEEE Microwave and Wireless Technology Letters, vol. 35, no. 5, pp. 617-620, May 2025. Authenticated DOI: 10.1109/LMWT.2025.3528863.

report_data.json: paper • reference/Kuo_2025_LMWT_paper.pdf

4. Circuit Diagram Done

Report Pages 4 & 18 • Figures 1 & 8

Figure 1 shows the 7-transistor DLATCH circuit diagram with device dimensions and pull-up loads. Figure 8 shows the 4-latch closed-loop ring with dual-clock phasing and alternating cross-connections. Generated by automated schematic drawing scripts.

figures/fig_circuit_latch.png • figures/fig_circuit_ring.png • scripts/draw_gpdk45_circuits.py

5. Theory and Working Principle Done

Report Page 5 • Theory Narrative

Full mathematical derivation of Kuo's Elmore delay equations (t_pdf = 4RC, t_pdr = 4RC), speed limit condition (2Td < TCK/2), and the physical distinction between edge-balance (R1 = Ron/2) and state regeneration. Establishes the 3·Ron/m stack heuristic.

report_data.json: theory

6. Tool & Technology Used Done

Report Page 6 • Environment Specifications

Cadence Virtuoso IC6.1.5, Cadence Spectre MMSIM 12.1, Cadence GPDK045 (45 nm standard-Vt CMOS, 1.0 V supply). Explicitly discloses the provenance of all figures (screenshots vs. Python plots from Spectre TSVs).

spectre/divider_gpdk45.scs • report_data.json: tool_technology

7. Simulator Based Circuit Implementation (Schematic) Done

Report Pages 6–8 • Figure 2 & Table 1

Figure 2 shows the genuine Cadence Virtuoso schematic editor window of the divider_core showing instances XD1 to XD4. Table 1 lists device parameters without sizing (m = 1, W = 240 nm, L = 45 nm, R = 8 kΩ).

screens/schematic_core_full.png • report_data.json: designs.without_sizing

8. Output Waveform Screenshot without Sizing Done

Report Page 9 • Figure 3

High-resolution Spectre transient waveform plot of the dividing unit-size baseline U8k (m = 1, R = 8 kΩ, vb = 1.0 V) dividing 1.4 GHz to 700.0 MHz. (The paper-rule non-dividing waveform is presented in Figure 9).

figures/fig_waveform_unsized.png • results/final/U8k.tsv

9. Circuit Based on Sizing Concept Done

Report Pages 10–11 • Figure 4 & Table 2

Figure 4 shows the Virtuoso DLATCH schematic with multiplier m = 4 and load R = 3 kΩ applied. Table 2 details sized dimensions: M1–M6 W = 240 nm × 4 (Weff = 960 nm), M7 W = 480 nm × 4 (Weff = 1920 nm, L = 90 nm).

screens/schematic_dlatch_full.png • report_data.json: designs.with_sizing

10. Output Waveform Screenshot with Sizing Done

Report Page 11 • Figure 5

Genuine Cadence ViVA waveform viewer screenshot of Design D at 1.4 GHz (tt corner, 27 °C, VDD = 1.0 V) demonstrating clean divide-by-two output at 700 MHz with 0.4344 V swing across all 8 phases.

screens/viva_tran_D_1p4GHz_full.png • results/final/D_1p4.raw

11. Values Table with Proof Figures Done

Report Page 12 • Table 3

Comprehensive performance comparison table (Unsized U8k vs. Sized Design D) listing Power (0.1375 vs 0.5413 mW), Delay (62.21 vs 25.99 ps), PDP (8.557 vs 14.067 fJ), Swing (0.2289 vs 0.4344 V), Phase Error (26.42° vs 38.46°), and M7 triode Vdsat margin, each paired with proof figure citations.

results/final/D_1p4.tsv • results/final/U8k.tsv • results/final/D_1p4.m7vdsat.txt

12. PVT Analysis Screenshot Done

Report Pages 13–15, 24–25 • Tables 4, 5, 6, 7 & Figures 6, 17, 18, 19, 23, 24

Exhaustive 45-corner matrix (5 process × 3 temps × 3 voltages). Design D passes 41/45 corners; Design B passes 21/45 corners; U8k baseline passes 26/45 corners; reference paper sizing passes 0/45 corners. Includes Python matplotlib pass/fail heatmaps and delay/power sweeps.

results/final/pvt_D.tsv • results/final/pvt_B6.tsv • results/final/pvt_U8k.tsv • pvt_summary_*.json

Diagram 4: 45-Corner PVT Matrix (5 Process × 3 Temperatures × 3 Voltages) & Automated Pass/Fail Check.

13. Layout Screenshot Done with caveat

Report Pages 16 & 25 • Figures 7 & 20

Figure 7 shows the genuine Cadence Virtuoso Layout XL editor view of divider_core with 4 DLATCH instances placed in a 2×2 bounding array. Figure 20 shows the internal DLATCH layout with 7 unit NMOS transistors and 2 poly resistors. Caveat: Layout is placement-only (unrouted).

screens/layout_core_full.png • screens/layout_dlatch_full.png • cadence/layout/build_layout_v2.il

14. Layout Simulator Waveform Screenshot Not possible (honest disclosure)

Report Page 16 • Narrative Statement

Heading is retained in strict accordance with the institutional template, but the body states plainly: "No post-layout simulation was performed because the physical layout is placement only, without routing, and the GPDK045 kit copy provides no Assura RCX extraction tech files."

Explicitly audited in COMPLETENESS_CHECK.md and FIXLOG.md

15. Any Other Relevant Information Done

Report Pages 16–27 • Figures 8–24

Rich engineering narrative covering: Figure 9 (paper sizing failure), Figure 10 (Design B 6 GHz waveform), Figure 11 (phase steps comparison), Figures 12–14 (M7 triode Vds vs Vdsat), Figure 15 (supply current transients), Figure 16 (frequency sweeps 1.4–7 GHz), Figure 21 (Assura DRC log), Figure 22 (standalone transient), and the Virtuoso vs standalone power gap.

report_data.json: other_info • results/final/analysis.json

16. Conclusion Done

Report Pages 27–28 • Section Conclusion

Summarizes successful 45 nm division for Design D (1.4 GHz, 41/45 pass) and Design B (6 GHz, 21/45 pass), explains the failure of reference paper sizing due to the stack regeneration boundary, notes M7 triode operation, and restates the placement-only layout status.

report_data.json: conclusion

17 & 18. Problems Faced and Problems Resolved Done

Report Page 28 • Troubleshooting Sections

Documents five authentic technical hurdles and their solutions: paper-rule regeneration failure (solved by 3·Ron/m heuristic), false division passes from 2·fin harmonics (solved by strict 0.1% ratio and 100 mV swing checker), M7 triode conduction (characterized via BSIM4 Vdsat), 32-bit Spectre compilation errors (resolved with host libraries), and automated routing DRC explosion (resolved by transparently reporting placement-only layout with 21 DRC errors).

report_data.json: problems_faced & problems_resolved

19 & 20. Any Other Comment & References Done

Report Page 29 • Comments and Citations

Details the 15.9% power difference between standalone (0.5413 mW) and Virtuoso schematic (0.4554 mW) netlists caused by layout-dependent effect parameters. Full references to Kuo et al. (IEEE MWTL 2025), Cadence GPDK045 v6.0, and Spectre MMSIM 12.1.

report_data.json: other_comment & references

21. Appendix: Complete PVT Tables Done

Report Pages 30–33 • Tables 8 & 9

Exhaustive tabular data for all 45 simulated corners for Design D (Table 8) and all 45 corners for the unit-size baseline U8k (Table 9), listing frequency, delay, power, PDP, and diagnostic failure notes for every single corner.

report/gpdk045/System_Design_Project_Report_gpdk045.pdf (Pages 30-33) • results/final/pvt_D.tsv • results/final/pvt_U8k.tsv

Section 04

What Happened, in Order

The authentic chronological journey of the project: from early ngspice attempts and Cadence VM crashes to 45 nm discovery, layout hurdles, and the v2 conference paper.

Phase 1 • Legacy Pre-Work

Early ngspice 180 nm Simulation Attempt

Initial architectural exploration began in ngspice using a generic LEVEL=1 180 nm model. While helpful for preliminary functional debugging, generic level-1 models lack physical short-channel velocity saturation, subthreshold conduction, and authentic BSIM4 mobility degradation. These ngspice results were strictly quarantined in legacy/ngspice/ and never used for reported 45 nm metrics.

Phase 2 • VM Environment Setup

Cadence VirtualBox VM Setup & Disk-Full Recovery

A VirtualBox CentOS 6 virtual machine hosting Cadence Virtuoso IC6.1.5 and Spectre MMSIM 12.1 was deployed with GPDK045 v6.0. During initial simulation sweeps, large Spectre raw binary waveforms exhausted guest disk capacity, causing kernel boot hangs on the virtual serial console (/dev/ttyS0). The VM was repaired, background VBoxSVC file-descriptor locking was mitigated via flock -o, and the environment was frozen into snapshot stable-v1.

Phase 3 • October 2026

GPDK045 Schematic Entry & First Netlist

The 7-transistor DLATCH and 4-latch divider core were entered into Cadence Virtuoso schematic editor using 45 nm standard-Vt transistors (nmos1v). The master netlist spectre/divider_gpdk45.scs was constructed with an initial unit device width of 240 nm and length of 45 nm at nominal 1.0 V supply.

Phase 4 • Oct 31, 2026

Discovery: Reference Paper Sizing Fails to Divide

Directly applying Kuo et al.'s rule R1 = Ron / 2 = 1.15 kΩ (with measured unit Ron = 2.3 kΩ) resulted in a striking failure: rather than dividing 1.4 GHz to 700 MHz, the output oscillated at 2799.8 MHz (2 · fin) with only 15.3 mV swing (Figure 9). The cross-coupled hold pair had insufficient loop gain to latch states across the series pull-down stack.

Phase 5 • Oct 31, 2026

Formulation of the 3·Ron/m Stack Heuristic & Sizing Search

Recognizing that the pull-down path comprises three stacked devices (M1/M3 + M5/M6 + M7), effective stack resistance is 3 · Ron / m (6.90 kΩ for m=1). Sweeping load resistance revealed that regeneration requires Rload ≥ 1.1 · 3·Ron / m (7.59 kΩ for m=1). This yielded the robust unsized baseline U8k (m=1, R=8 kΩ). Increasing width to multiplier m=4 reduced stack resistance to 1.72 kΩ, opening the door to lower load resistances: Design D (m=4, R=3 kΩ) and Design B (m=4, R=2 kΩ).

Phase 6 • Oct 31, 2026

Tail Transistor Triode Diagnosis

Spectre transient operating point evaluation of tail device M7 revealed that its drain voltage remains between 8.1 mV and 66.9 mV throughout switching, far below its extracted BSIM4 saturation voltage Vdsat = 357.8 mV. Across all designs, M7 operates in deep triode due to compressed 1.0 V supply headroom. The report and theory assignment were corrected to state triode operation honestly.

Phase 7 • Oct 31, 2026

Comprehensive 45-Corner PVT Sweep Campaigns

Deterministic 45-corner simulation campaigns (5 corners × 3 temps × 3 voltages) were executed in Spectre MMSIM 12.1. Design D demonstrated robust commercial margin with 41 of 45 corners passing (failing only under combined 125 °C and 0.9 V). Design B achieved 21 of 45 passing corners at 6.0 GHz. The U8k baseline passed 26 of 45 corners, while the paper-rule sizing passed 0 of 45 corners.

Phase 8 • Oct 31, 2026

Layout Implementation & Routing DRC Explosion

Physical layout was designed in Cadence Virtuoso Layout XL. While cell placement was clean, running the automated Cadence router on the 4-latch core produced an explosion of 134 DRC errors and severe LVS shorts. Rather than masking the issue, the team made an honest engineering decision: quarantine the routed attempt and present the clean, unrouted placement layout with exactly 21 documented Assura DRC errors across 3 rules.

Phase 9 • Nov 1, 2026

Investigation of the 15.9% Power Gap

A discrepancy was detected between standalone Spectre netlist power (0.5413 mW) and Virtuoso schematic netlist power (0.4554 mW) for Design D. Isolated parameter injection in power_gap_experiment.md proved this was not an error: Virtuoso's CDF netlister automatically computes layout-dependent effect (LDE) parameters (mechanical stress terms sa/sb/sd, well-proximity sca/scb/scc, and diffusion parasitics), shifting device currents by 15.9%. Both values were retained and documented.

Phase 10 • Nov 1–2, 2026

Lab Report Rebuild & Theory Assignment Compilation

Deliverables for Dr. Kaveri Hatti's evaluation were compiled. The System Design Lab Report was rebuilt to 33–35 pages with 24 verified figures and full PVT appendices. The 7-page Theory Assignment (23ECE302_Theory_Assignment.pdf) was compiled with Elmore derivations, stack heuristics, and traceability tables.

Phase 11 • Nov 2, 2026

V2 Academic Research Paper Sprint

Building upon the course baseline, the team launched the v2 preprint and conference paper sprint. Preregistered protocols E1–E7 uncovered the fundamental mathematical pair law: adjacent phase errors alternate as E = |45° - 180° · δ · fin| across all dividing runs. Mismatch Monte Carlo simulations revealed that operating near the 6 GHz speed limit collapses under transistor threshold mismatch (only 1/200 mismatch-only runs divide at 6 GHz), defining the core thesis for IEEE conference submission.

Section 05

How to Explain It in a Viva

15 likely examiner questions with concise, technically rigorous answers formatted as interactive accordions.

1. Why does the circuit use four latches instead of two?

A conventional divide-by-two divider uses two latches to produce quadrature (4-phase) outputs. Cascading four latches in a closed ring with dual-clock phasing and alternating cross-connections introduces an odd loop inversion requiring two full input clock periods (2·TCK) for a complete cycle. This quadruples the number of output taps from 4 to 8, providing eight discrete 45° phase outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°) without requiring bulky polyphase filters or input frequency quadruplers.

Viva Tip: Emphasize that each latch adds delay Td ≈ TCK / 8, so 8 outputs naturally correspond to 8 equal phase steps around 360°.

2. How do the eight phases arise topologically?

Each latch (XD1 to XD4) has differential outputs (Q, Qb), giving 4 × 2 = 8 output nodes: Q1 (0°), Q2 (45°), Q3 (90°), Q4 (135°), Q1b (180°), Q2b (225°), Q3b (270°), and Q4b (315°). Dual clocking ensures that when CK is high, Latches 1 & 4 sample while 2 & 3 hold; when CK falls low, Latches 2 & 3 sample while 1 & 4 hold. Inter-stage connections alternate between crossed and direct polarity, ensuring stable 45° phase propagation around the ring.

3. What is on-resistance (Ron) and how was it determined in GPDK045?

On-resistance (Ron) is the effective channel resistance of an NMOS transistor operating in deep triode: Ron = Vds / Ids under nominal gate bias (Vgs = 1.0 V). In Cadence GPDK045 at 45 nm, Spectre DC operating point sweeps on a unit NMOS transistor (W = 240 nm, L = 45 nm) yield Ron = 2.3 kΩ (spanning 2.28 kΩ to 2.73 kΩ across process corners).

4. Why did Kuo et al. select R1 = Ron / 2 in their paper?

Kuo et al. applied an Elmore RC delay model assuming the tail transistor M7 drain was at AC ground. Under this assumption, discharging through the sampling branch yields fall delay t_pdf = (8C)·(Ron/2) = 4·Ron·C, while charging through pull-up load R1 yields rise delay t_pdr = (8C)·R1. Equating t_pdr = t_pdf produces R1 = Ron / 2 to balance rise and fall edge transitions and achieve 50% duty cycle symmetry.

Viva Tip: Make sure to point out that this is strictly an EDGE-BALANCE condition, not a regeneration condition.

5. Why did the paper's sizing rule (R1 = 1.15 kΩ) fail to divide in 45 nm?

In 45 nm GPDK045, Ron = 2.3 kΩ, so the paper's rule sets R1 = 1.15 kΩ. However, the physical pull-down path consists of three stacked NMOS transistors (M1/M3 + M5/M6 + M7) with total stack resistance 3·Ron = 6.90 kΩ. A load resistor of only 1.15 kΩ provides small-signal loop gain A_loop = gm · R1 << 1 in the cross-coupled hold pair. Without regenerative gain, the circuit cannot latch digital states; it simply passes clock feedthrough, oscillating at 2799.8 MHz (2·fin) with a tiny 15.3 mV swing.

6. What is the stack-regeneration heuristic and how was it derived?

To overcome the pull-down stack resistance and guarantee gm · Rload > 1 for regeneration, load resistance must scale with the total stack impedance: Rload ≥ 1.1 · (3·Ron / m), where m is the device multiplier. For unit size (m=1), the heuristic predicts Rload ≥ 7.59 kΩ (verified by Spectre sweeps showing division onset between 6 and 7 kΩ; R = 8 kΩ was chosen). For m=4, stack resistance drops to 1.72 kΩ, allowing lower loads: Design D uses R = 3 kΩ and Design B uses R = 2 kΩ.

7. Why use Current-Mode Logic (CML) instead of static CMOS?

CML operates with reduced differential voltage swings (100–450 mV) rather than full rail-to-rail transitions. This provides several major advantages: much higher maximum operating frequency (gigahertz range), significantly lower dI/dt switching noise on power and ground rails, natural differential complementary outputs, and predictable propagation delays essential for precise multiphase clock spacing.

8. What is PVT analysis and what was your evaluated matrix?

PVT stands for Process, Voltage, and Temperature variation analysis. We simulated a full 45-corner matrix comprising: 5 Process Corners (typical-typical 'tt', fast-fast 'ff', slow-slow 'ss', fast-slow 'fs', slow-fast 'sf') × 3 Temperatures (-40 °C industrial cold, +27 °C nominal, +125 °C industrial hot) × 3 Supply Voltages (0.9 V low [-10%], 1.0 V nominal, 1.1 V high [+10%]). Total: 5 × 3 × 3 = 45 corners.

9. Why are there two different power numbers for Design D (0.5413 mW vs 0.4554 mW)?

0.5413 mW is the power simulated from the standalone Spectre netlist with default BSIM4 device parameters. 0.4554 mW is from the Cadence Virtuoso schematic CDF netlist. This authentic 15.9% difference arises entirely from layout-dependent effect (LDE) parameters computed by Virtuoso: mechanical stress (sa, sb, sd), well-proximity effects (sca, scb, scc), and diffusion parasitics (as, ad, ps, pd), which alter threshold voltages and drain currents. Injecting these parameters into the standalone netlist matches the Virtuoso OCEAN result within 0.02%.

10. What does 'placement-only layout' mean and why does it have 21 DRC errors?

'Placement-only layout' means the transistor active areas, poly gates, contacts, and resistors were placed as genuine Cadence GPDK045 pcells in Virtuoso Layout XL, but no routing metallization was finalized. The 21 Assura DRC errors consist of 1 error on Rule 220, 6 errors on Rule 221 (unconnected well tap spacings matching the 0.755 µm device pitch), and 14 errors on Rule 595 (isolated Metal1 contact pads in transistor rows). Running an automatic router produced 134 DRC errors, so the clean placement was preserved honestly.

11. Why was post-layout simulation not performed?

Post-layout simulation requires two prerequisite steps: an LVS-clean routed layout and parasitic extraction technology rule decks (Assura RCX or Quantus QRC). In our academic environment, automated routing produced DRC/LVS violations, and the installed GPDK045 copy lacks Assura RCX extraction tech files. Therefore, post-layout simulation was physically impossible, and claiming post-layout performance would violate academic integrity.

12. What operating region is tail transistor M7 operating in, and why?

M7 operates in the TRIODE (linear) region, not saturation. Its transient drain voltage peaks at only 66.9 mV in Design D (and 76.8 mV in Design B), remaining far below its BSIM4 saturation voltage Vdsat = 357.8 mV. With a nominal supply of only 1.0 V and voltage drops across load resistors (≈ 200–400 mV) and switching transistors (≈ 400–500 mV), there is insufficient drain-to-source headroom to keep M7 saturated.

13. What is the fundamental engineering trade-off between Design D and Design B?

Design D operates at 1.4 GHz input with R = 3 kΩ, prioritizing division margin and robustness: it achieves 0.4344 V swing and passes 41/45 PVT corners (91.1%), but has a larger phase-step error of 38.46°. Design B operates at 6.0 GHz with R = 2 kΩ, operating close to the divider speed limit where 2·Td ≈ TCK/4: it achieves an excellent 3.78° phase error (matching the literature benchmark), but exhibits smaller swing (0.1349 V) and lower PVT corner coverage (21/45 corners pass).

14. What is the key scientific insight discovered in the v2 research paper?

The v2 paper discovered that in nominal 4-latch rings, adjacent phase steps alternate in pairs summing to 90°, governed by the exact relation: E = |45° - 180° · δ · fin|, where δ is latch delay. Phase error drops to zero only as frequency approaches the division speed limit. However, device mismatch destroys this mechanism: under Monte Carlo process-and-mismatch statistics, Design B's 6 GHz division collapses (only 1/200 mismatch-only runs divide), proving that tight phase accuracy and division margin rarely coexist in uncalibrated silicon.

15. How did you verify results to guarantee zero fabricated numbers?

Every number cited in the report, theory assignment, and presentation is traceable to an authenticated simulation output in results/final/ (e.g. D_1p4.tsv, B_6g.tsv, pvt_D.tsv). All claims are cataloged with rerun commands in plan/claims_register.csv. No numbers from legacy 180 nm drafts were imported, and automated checkers verify that manuscript numbers match raw simulation files exactly.

Section 06

Where to Find Things

Repo-relative paths for all primary documents, simulation evidence files, Cadence netlists, and verification logs.

File / Folder Path (Repo-Relative)	Document / Evidence Content	Key Metrics / Role
report/gpdk045/System_Design_Project_Report_gpdk045.pdf	23ECE383 Lab System Design Project Report	33–35 pages, 24 figures, full PVT tables
report/gpdk045/theory/23ECE302_Theory_Assignment.pdf	23ECE302 VLSI Theory Assignment Report	7 pages, Elmore delay, sizing proof tables
report/gpdk045/report_data.json	Master Structured JSON Data Source	All text, table rows, and metrics for builders
report/gpdk045/COMPLETENESS_CHECK.md	Academic Format & Rubric Audit	Exhaustive compliance check against Kaveri Hatti rubric
report/gpdk045/FIXLOG.md	Audit Finding Resolution Log	Detailed tracking of all 28 audit fixes (C1–C4, I1–I11)
results/gpdk045/final/D_1p4.tsv	Design D Raw Spectre Simulation Results	1.4 GHz, 0.5413 mW, 25.99 ps, 38.46° error
results/gpdk045/final/B_6g.tsv	Design B Raw Spectre Simulation Results	6.0 GHz, 0.4929 mW, 27.94 ps, 3.78° error
results/gpdk045/final/U8k.tsv	Unsized Baseline U8k Simulation Results	m = 1, R = 8 kΩ, 0.1375 mW, 62.21 ps, 26.42°
results/gpdk045/final/unsized.tsv	Paper Rule Failure Simulation Results	m = 1, R = 1.15 kΩ: fails (2799.8 MHz, 15.3 mV)
results/gpdk045/final/pvt_D.tsv & pvt_summary_D_1p4.json	Design D 45-Corner PVT Sweep	41/45 pass; fails only at 125 °C, 0.9 V
results/gpdk045/final/pvt_B6.tsv & pvt_summary_B_6g.json	Design B 45-Corner PVT Sweep	21/45 pass at 6.0 GHz
results/gpdk045/final/pvt_U8k.tsv & pvt_summary_U8k_1p4.json	U8k Baseline 45-Corner PVT Sweep	26/45 pass at 1.4 GHz
results/gpdk045/assura_drc_dlatch_summary.txt	Assura DRC Execution Summary	21 DRC errors across Rules 220, 221, 595
spectre/divider_gpdk45.scs	Master Standalone Spectre Netlist	Core 4-latch divider netlist in GPDK045
paper/manuscript_v2.tex	v2 Conference Manuscript LaTeX Draft	ISQED/NEWCAS target paper draft
plan/claims_register.csv	Master Verified Claims Register	Every paper claim with evidence file and rerun cmd
plan/NICHE_DECISION.md	v2 Research Strategic Niche Decision	Scientific thesis, claim tiers, and novelty analysis

Section 07

Glossary

30 fundamental terms in VLSI design, frequency division, and multiphase clocking explained clearly.

Current-Mode Logic (CML)

A differential logic family that steers constant bias current through differential pairs into resistive pull-up loads, producing small-swing, ultra-fast switching.

D-Latch

A level-sensitive bistable circuit that tracks input data when its clock signal is active (sample mode) and holds output state when clock is inactive (hold mode).

Frequency Divider (Prescaler)

A circuit that takes an input clock of frequency fin and produces an output clock of frequency fout = fin / N. Here, N = 2.

Multiphase Clocks

A set of clock signals operating at the identical frequency but offset in time by equal phase angles (e.g. 8 phases spaced by 45°).

Quadrature Clocks

A 4-phase clock system with phases separated by 90° (0°, 90°, 180°, 270°), typically used in I/Q modulators and demodulators.

Ring Divider

A frequency divider constructed by cascading multiple latch stages in a closed circular loop with net feedback inversion.

Dual-Clock Phasing

Clocking interleaved latch stages with complementary clocks (CK and CKb) so adjacent stages alternate between sampling and holding.

Alternating Cross-Connection

Alternating between direct (Q→D, Qb→Db) and crossed (Qb→D, Q→Db) inter-stage couplings to maintain proper differential signal polarity and loop inversion.

Net Loop Inversion

An odd total number of signal inversions around a closed circuit loop, preventing latch-up and forcing continuous divide-by-two oscillation.

Propagation Delay (Td or δ)

The time interval required for a transition at the latch input to propagate to the output during sampling mode.

Speed Limit (2·Td < TCK/2)

The maximum input frequency constraint: signals must traverse two cascaded latches within half an input clock cycle for valid division.

Elmore Delay Model

A first-order RC network approximation that computes circuit propagation delay by summing the resistance-capacitance products along discharge paths.

On-Resistance (Ron)

The channel resistance of a MOS transistor operating in deep triode, defined as Vds / Ids under full gate overdrive. (2.3 kΩ in GPDK045).

Edge-Balance Condition

Setting load resistance R1 = Ron / 2 to equalize rising and falling transition times (tpdr = tpdf) under a simplified grounded-tail Elmore model.

Stack-Regeneration Heuristic

The sizing guideline Rload ≥ 1.1 · (3·Ron / m) ensuring load resistance provides sufficient loop gain (gm·R > 1) across three stacked NMOS devices.

Small-Signal Loop Gain (A_loop)

The round-trip gain gm·Rload around the cross-coupled hold pair; must exceed 1.0 to regenerate and maintain stored digital states.

Power-Delay Product (PDP)

The product of average DC power consumption and propagation delay (PDP = Power · Delay), measuring energy consumption per switching event (in fJ).

Phase-Step Error

The maximum angular deviation between adjacent output clock edges from the ideal 45.0° equidistant spacing around a full 360° output period.

Differential Voltage Swing

The difference between the high and low voltage levels of an output signal (Vswing = Vhi - Vlo); must be ≥ 100 mV for valid logic detection.

PVT Corners

A verification matrix simulating circuits across Process corners (tt, ff, ss, fs, sf), Supply Voltages (±10%), and Operating Temperatures (-40 to +125 °C).

Process Corner

Manufacturing variations in NMOS and PMOS speed: typical (tt), fast (ff), slow (ss), or skewed cross-corners (fs, sf).

Saturation Voltage (Vdsat)

The drain-to-source voltage threshold above which channel pinch-off occurs and drain current saturates. (357.8 mV for M7 in GPDK045).

Triode Region (Linear Region)

The operating regime where Vds < Vdsat. Tail transistor M7 operates in triode because its peak Vds is only ~67 mV, below Vdsat.

Design Rule Check (DRC)

Physical design verification ensuring layout geometric features (widths, spacings, enclosures) comply with foundry manufacturing rules.

Layout Versus Schematic (LVS)

Verification confirming that physical layout devices and net connections match the intended circuit schematic topology exactly.

Parasitic Extraction (PEX / RCX)

Extracting actual parasitic resistances and capacitances from routed physical layout masks into a back-annotated simulation netlist.

Placement-Only Layout

A physical layout where device pcells are placed on grid with active/poly DRC compliance, but interconnect routing metal is omitted.

Layout-Dependent Effects (LDE)

Variations in transistor performance caused by proximity to well edges (WPE) and mechanical stress from shallow trench isolation (STI).

Monte Carlo Simulation

Statistical circuit simulation evaluating the impact of random microscopic transistor mismatches (threshold voltage, channel length) on performance.

Figure of Merit (FoM)

A standardized metric comparing divider efficiency: typically defined as Frequency Tuning Range (FTR %) / Power (mW).